The present invention generally relates to semiconductor, and more particularly, to a high-K metal gate MOS semiconductor devices.
As processes for fabricating complementary metal-oxide-semiconductor (CMOS) develop, scaling efforts of CMOS and MOS devices have moved to high-k dielectric materials that have dielectric constants greater than 3.9 of silicon dioxide and metal gate structures have replaced polysilicon gate structures.
FIG. 1 shows a cross-sectional view of a prior art MOS device including a sidewall dielectric layer 140, a sacrificial gate electrode 110, a covering layer 120 overlying the sacrificial gate electrode and an interlayer dielectric layer 130 overlying the covering layer.
FIG. 2 shows a cross-sectional view of the prior art device of FIG. 1, wherein a portion of the interlayer dielectric layer 130 has been removed to expose a portion of the covering layer 120. The portion of the interlayer dielectric layer can be removed using Chemical Mechanical Polishing (CMP). As shown in FIG. 3, while removing a portion of the covering layer to expose a portion of the sacrificial gate electrode, erosion 150 occurs at the edges of the interlayer dielectric layer adjacent to the covering layer. It is believed that the edges of the interlayer dielectric layer can be polished much faster than other surface areas of the interlayer dielectric layer. In addition, erosion may also occur on the surface portion of the sidewall dielectric layer that is disposed between the covering layer and the sacrificial gate electrode during the removal of the sacrificial gate electrode. For example, the sacrificial gate electrode can be removed by exposing it to a solution comprising between about 20 to about 30 percent Tetramethylammonium Hydroxide (TMAH) by volume in deionized water. FIG. 4 shows a cross-sectional view of FIG. 3 after the sacrificial gate electrode is removed. A subsequent metal deposition to fill a trench 160 left after the removal of the sacrificial gate electrode may also fills the erosion spaces, and thus affects the insulation characteristics of the interlayer dielectric layer and the performance of the device. This process has been described in U.S. Pat. No. 7,183,184 that discloses a method for making a semiconductor device having a metal gate electrode. However, it should be noted that examples cited in the patent do not provide adequate performance.
Accordingly, it would be desirable to have a method for fabricating a high-k metal gate electrode MOS device that reduces or eliminates erosion in a dielectric layer in a polishing process.